Patent
1994-12-21
1997-07-22
Harvey, Jack B.
395484, 395496, G06F 1200
Patent
active
056511388
ABSTRACT:
A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).
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Eifert James B.
Harwood, III Wallace B.
Le Chinh Hoang
Harvey Jack B.
Motorola Inc.
Pancholi Jigar
Polansky Paul J.
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