Data processor with branch target address cache and subroutine r

Details Data processor with branch target address cache and subroutine r Data processor with branch target address cache and subroutine r

1996-09-23

1997-11-11

Kim, Matthew M.

395403, 395450, G06F 1208

Patent

active

056873492

ABSTRACT:
A data processor (10) has a branch and link address cache (.sup.++ BLAC.sup.++) (40) and a Branch Target Address Cache (BTAC) (48) for storing a number of recently encountered fetch address-target address pairs. The BLAC buffers data pairs identifying corresponding subroutine call and subroutine return instructions each time data processor executes a particular subroutine. Upon the second call of the subroutine, control logic (44) stores the half of the data pair identifying the subroutine return instruction and data identifying the return address in the BTAC. The data processor is thereby able to predict the target address of a subroutine return instruction as it is able to predict the target address of traditional branch instructions.

REFERENCES:
patent: 5426764 (1995-06-01), Ryan
patent: 5619662 (1997-04-01), Steely, Jr. et al.

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