Data processor with branch target address cache and method of op

Details Data processor with branch target address cache and method of op Data processor with branch target address cache and method of op

1994-04-15

1996-06-25

Lane, Jack A.

395375, G06F 932

Patent

active

055308252

ABSTRACT:
A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry. A branch unit (20) generates an execution address that depends upon one of the plurality of instructions. After executing each instruction, the branch unit may delete an entry from the BTAC if the instruction's execution address differs from the target address and if the instruction is the same instruction which generated the BTAC entry initially.

REFERENCES:
patent: 5142634 (1992-08-01), Fite et al.

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