Data processor with branch target address cache and method of op

Details Data processor with branch target address cache and method of op Data processor with branch target address cache and method of op

1996-09-23

1998-09-08

Lane, Jack A.

G06F 932

Patent

active

058058770

ABSTRACT:
A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit predicts whether the condition precedent will be met the next time it encounters the same branch instruction. If the predicted value of the condition precedent would cause the branch to be taken, then the branch unit adds the fetch address-target address pair corresponding to the branch instruction to the BTAC. If the predicted value of the condition precedent would cause the branch to be not taken, then the branch unit deletes the fetch address-target address pair corresponding to the branch instruction from the BTAC.

REFERENCES:
patent: 4200927 (1980-04-01), Hughes et al.
patent: 5101341 (1992-03-01), Circello et al.
patent: 5230068 (1993-07-01), Van Dyke et al.
patent: 5442756 (1995-08-01), Grouchowski et al.
PowerPC 601 RISC Microprocessor User'Manual (MPC601UM/AD;52G7484;MPR601UMU-02), IBM Microelectronics and Motorola, 1993.

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