Data processor with an integer multiplication function on a frac

Details Data processor with an integer multiplication function on a frac Data processor with an integer multiplication function on a frac

1991-04-02

1994-11-08

Envall, Jr., Roy N.

Boots, shoes, and leggings

3647505, 364736, G06F 752, G06F 1538

Patent

active

053633229

ABSTRACT:
A data processing system (10) which primarily supports fractional multiplication operations has a multiplication logic circuit (20) for executing integer multiplication functions efficiently. During an integer multiplication function, two multiplicands are multiplied together as if the multiplication function was fractional. A predetermined accumulation input is stored and shifted to the right by a Right Shift Logic circuit (32) before being added to a product of the two multiplicands. An accumulated product of the multiplication function is formed by an adder (36) and shifted to the left by a Left Shift Logic circuit (38) until the accumulated product is in integer form. Implementing an integer multiplication operation with a fractional multiplier in the data processing system requires a single software instruction.

REFERENCES:
patent: 4594678 (1986-06-01), Uhlenhoff
patent: 4597053 (1986-06-01), Chamberlin
patent: 4841467 (1989-06-01), Ho et al.
patent: 4876660 (1989-10-01), Owen et al.
patent: 4958312 (1990-09-01), Ang et al.
Motorola DSP56116 Digital Signal Processor User's Manual, Oct. 1990. Page Numbers 3-6-3-9, A-98-A-101, A-120,121, A-158, 159.
Proceedings ICASSP 90, 1990 International Conference On Acoustics, Speech, and Signal Processing, Apr. 3-6, 1990, IEEE Signal Processing Society.
Nov. 5, 1990 Press Release Statements from Motorola, Inc., Spectrum Signal Processing, Inc., Ariel Corporation, and Mentor Graphics.

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