Data processor with addressing mode decoding function

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395425, 3642624, 3642628, 3642551, G06F 922

Patent

active

051230968

ABSTRACT:
A data processor which is so constructed that an operation code decoder decodes an operation code in an instruction to be processed comprising an operation code and an operand descriptor, and an addressing mode decoder decodes the operand descriptor, so that when the addressing mode of the operand is detected to be a specified addressing mode, for example, a register direct addressing mode, an entry address of microinstruction generated by the operation code decoder is modified, thereby enabling the entry address, different in microinstruction during the specified addressing mode and others, to be generated without increasing the number of product terms of a PLA in an instruction decoder.

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