Boots – shoes – and leggings
Patent
1977-10-25
1979-07-24
Springborn, Harvey E.
Boots, shoes, and leggings
G06F 300, G06F 900
Patent
active
041625196
ABSTRACT:
All instruction words of a microprocessor have the same number of instruction word bits, but the number of instruction word bits constituting address bits varies as a function of the number of addresses associated with the operation specified by the operation code part of the instruction word. Operations having only one associated address have no address bits. A translator circuit has a plurality of inputs each receiving one bit of the instruction word, a set of control outputs for furnishing control signals, and a set of address outputs for furnishing address words. The set of control outputs has logic interconnections with each of the translator circuit inputs, as does the set of address outputs. Operation code bits in the instruction word are therefore also utilized as address bits, thereby decreasing the total number of instruction word bits required. For some operations, the required address is an operand stored in a memory location addressed by the operation code bits of the instruction word. This operand is read out and used as an address for the memory.
REFERENCES:
patent: 3389376 (1968-06-01), Packard
patent: 3736567 (1973-05-01), Lotan
patent: 3990054 (1976-11-01), Perlowski
Nixdorf Computer AG
Rich Marianne
Springborn Harvey E.
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