Data processor with a multi-level protection mechanism, multi-le

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Details

395478, 395479, 395483, 395485, 395405, G06F 1214

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active

056491590

ABSTRACT:
A data processor (30) includes a multi-level protection circuit (50) which enables the generation of external control signals. The multi-level protection circuit (50) defines regions of protection (41, 42), which may be nested. The protection circuit (50) checks access cycle attributes such as read or write, supervisor or user, and data or instruction. First (51) and second (54) decoders are associated with each other and define two regions (41, 42) which may overlap. When a CPU (31) accesses a memory location within both regions, the protection attributes of the second decoder (54), at a higher priority level than the first decoder (51), control. If an attempted access violates the programmable protection attributes of the second region (42), then the multi-level protection circuit (50) prevents the access from occurring, even though the access attributes of the first decoder (51) alone would enable the access. The protection circuit (50) thus allows the use of high-density memory or peripheral devices for multiple purposes.

REFERENCES:
patent: 4099243 (1978-07-01), Palumbo
patent: 4926316 (1990-05-01), Baker et al.
patent: 4949238 (1990-08-01), Kamiya
patent: 5151986 (1992-09-01), Langan et al.
patent: 5263146 (1993-11-01), Mishima
patent: 5317717 (1994-05-01), Cutlet et al.
Motorola, Inc., "MC68040, MC68EC040, MC68LC040 Microprocessors User's Manual," 1992, pp. 3-29 through 3-30.
Motorola, Inc., "MC68332 User's Manual-System Integration Module," 1990, pp. 4-27 through 4-46.

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