Data processor using indirect register addressing

Details Data processor using indirect register addressing Data processor using indirect register addressing

2002-07-29

2004-02-03

Tokar, Michael (Department: 2819)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C711S202000, C711S214000, C712S220000, C712S225000

Reexamination Certificate

active

06687808

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processor. More particularly, the present invention relates to a data processor using indirect addressing of registers.
2. Description of the Related Art
Operation frequencies of data processors have been recently increased while access times to memories have been decreased. This situation increases a need for reducing in access times of memories.
A technique is widely used in which a part of a working set within data on a memory is stored in a register to thereby reduce an access time of a memory. However, this technique requires an increase in the number of the registers to reduce the memory access. The increase of the registers prolongs instruction words and thus increases the amount of accesses needed for executing the instructions. Hence, the conventional technique encounters a demerit from the viewpoints of the performance ability and the cost.
When data stored in a register is processed by a data processor, data conversion is often requested.
FIG. 1
shows a typical process of executing an instruction accompanied by data conversion. The instruction is executed in the three phases: a pre-operation data conversion (S
101
), an operation (S
102
) and a post-operation data conversion (S
103
). The pre-operation conversion (S
101
) is composed of a register read (S
111
), a data conversion (S
112
) and a register write (S
113
). The operation (S
102
) is composed of a register read (S
114
), an operation (S
115
) and a register write (S
116
). The post-operation conversion (S
103
) is composed of a register read (S
117
), a data conversion (S
118
) and a register write (S
119
).
A process of executing an instruction includes instruction fetch IF, instruction decode ID, instruction execution EX, data forward DF and data write WB.
The instruction fetch IF is an action for reading out an instruction word from a main memory and transiently storing the instruction word in an instruction register.
The instruction decode ID is an action for decoding the instruction word. At first, an operation is specified on the basis of the operation code in the instruction word, and then a pre-operation data conversion is specified, and a post-operation data conversion is specified. Furthermore, a register address specifying a register for storing the operation result is specified on the basis of the operand field(s) of the instruction word.
The instruction execution EX is an action for executing an operation on the operand data. The data forward DF is an action for forwarding the operation result to a buffer and transiently storing the operation result therein. The write WB is an action for writing the operation result stored in the buffer to the specified register of the register file.
Data processors are often pipelined to improve the processing ability. In such data processors, executions of instructions are overlapped to increase the effective operation speed.
FIG. 2
shows a typical pipelining technique. To execute an instruction, instruction fetch IF, instruction decode ID, instruction execution EX, e data forward DF, and the data write WB are sequentially executed.
To execute a next instruction, instruction fetch IF for the next instruction is executed in parallel with the instruction decode ID for the previous instruction. Then, instruction decode ID for the next instruction is executed in parallel with the instruction execution EX for the previous instruction. Next, instruction execution EX for the next instruction is executed in parallel with the data forward DF of the previous instruction. And, data forward DF for the next instruction is then executed in parallel with the write WB for the previous instruction. Finally, data write WB for the next instruction is executed.
If the next instruction has a dependence on the previous instruction, the operation result obtained by the instruction execution EX for the previous instruction can be forwarded during the instruction decode ID for the next instruction word. As a result, each of the instruction words can be executed substantially in one clock cycle.
However, execution of an instruction that requests data conversion degrades the processing ability of pipelined data processors.
FIG. 3
shows a process of executing an instruction requesting a pre-operation data conversion in a pipelined data processor. An instruction accompanied by the pre-operation data conversion is separated into a data conversion instruction and an operation instruction. Firstly, instruction fetch IF, instruction decode ID, instruction execution EX, data forward DF, and data write WB are executed for the data conversion instruction.
Instruction fetch IF for the operation instruction is executed in parallel with the instruction execution EX for the data conversion instruction. This means one clock cycle is wasted. Instruction decode ID for the operation instruction is then executed in parallel with the data forward DF for the data conversion instruction, and instruction execution EX is executed in parallel with the data write WB for the previous instruction word. After that, data forward DF and data write WB are executed for the operation instruction.
To execute a next instruction, instruction fetch IF for the next instruction is executed in parallel with the instruction decode ID of the operation instruction of the previous instruction. Instruction decode ID for the next instruction is then executed in parallel with the instruction execution EX for the operation instruction. Instruction execution EX for the next instruction is executed in parallel with the data forward DF for the operation instruction, and the data forward DF for the next instruction is executed in parallel with the data write WB for the operation instruction. After that, the data write WB for the next instruction is executed.
When the next instruction has a dependence on the previous instruction word, the operation result produced by the instruction execution EX for the operation instruction is forwarded during the instruction decode ID for the next instruction word. This implies that it takes three clock cycles for an instruction accompanied by the pre-operation data conversion to be executed.
FIG. 4
shows a process of executing an instruction accompanied by post-operation data conversion in a typical pipelined data processor. The instruction accompanied by the post-operation data conversion is separated into an operation instruction and a data conversion instruction. Instruction fetch IF, instruction decode ID, instruction execution EX, data forward DF and data write WB are sequentially executed for the operation instruction.
The instruction fetch IF for the data conversion instruction is executed in parallel with the instruction decode ID for the operation instruction. The instruction decode ID is then executed in parallel with the instruction execution EX for the operation instruction, and then the instruction execution EX is executed in parallel with the data forward DF for the operation instruction. Next the data forward DF is executed in parallel with the data write WB for the operation instruction. Finally, the data write WB for the data conversion instruction is executed. The operation result produced by the instruction execution EX for the operation instruction word is forwarded during the instruction decode ID for the data conversion instruction.
To execute a next instruction, the instruction fetch IF for the next instruction is executed in parallel with the instruction decode ID for the data conversion instruction. Next the instruction decode ID is executed in parallel with the instruction execution EX for the data conversion instruction, and then the instruction execution EX is executed in parallel with the data forward DF for the data conversion instruction. The data forward DF is then executed in parallel with the data write WB for the data conversion instruction. Finally, the data write WB for the next instruction is finally executed. It takes substantially two clock cycles for the instr

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