Data processor using FIFO memories for routing operations to par

Details Data processor using FIFO memories for routing operations to par Data processor using FIFO memories for routing operations to par

1994-12-12

1997-10-07

Teska, Kevin J.

Boots, shoes, and leggings

3642599, 364258, 364259, G06F 900

Patent

active

056757760

ABSTRACT:
The device is adapted more particularly to process programs written in FORTH. The device includes a) a program memory (1) storing instruction data, b) an operational unit (15) comprising a plurality of operational means (16, 17, 18), c) a central decoding unit (35), and d) a stack memory (8) for the return instructions.

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patent: 4734850 (1988-03-01), Tonii et al.
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patent: 4980821 (1990-12-01), Koopman et al.
patent: 5070451 (1991-12-01), Moore et al.
patent: 5179734 (1993-01-01), Candy et al.
patent: 5301340 (1994-04-01), Cook
The Journal of Forth Application and Research, vol. 2, No. 1, 1984, J.C. Vaughan, R.L. Smith, "The Design of a Forth Computer", pp. 49-64.

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