Data processor unit comprising a control section which comprises

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G06F 922

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active

047501081

ABSTRACT:
A data processor unit comprising an instruction register for temporary storing a macro-instruction having at least an opcode part and being supplied thereto, and a control section which comprises a sequencer and a microcode memory connected to each other. In said microcode memory there being stored a number of handlers each comprising a number of micro-instruction words. For each opcode there is provided a dedicated handler. The micro-instruction words of handler forming a microroutine for controlling the execution of at least part of a processor action indicated by the corresponding opcode. A handler being addressed by an address generator included in the sequencer and under control of his appertaining opcode.

REFERENCES:
patent: 3990054 (1976-11-01), Perlowski
patent: 3991404 (1976-11-01), Brioschi
patent: 4038643 (1977-07-01), Kim
patent: 4126896 (1978-11-01), Yamazaki
patent: 4173041 (1979-10-01), Dvorak et al.
patent: 4179737 (1979-12-01), Kim
Tanenbaum, "Structured Computer Organization", 1976, Prentice-Hall, pp. 74 & 69.

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