Data processor system for preloading/poststoring data arrays pro

Details Data processor system for preloading/poststoring data arrays pro Data processor system for preloading/poststoring data arrays pro

1995-12-21

1998-05-19

Treat, William M.

39580002, 395872, G06F 1338

Patent

active

057548765

ABSTRACT:
Preload register groups are respectively provided for the plurality of scalar processors which execute iterative processing in distributed manner. Each group consists of preload registers corresponding to a plurality of data arrays that appear in the iterative processing. According to address information about the plurality of arrays to be preloaded specified by any of the processors, a preload control unit reads partial data groups of one of the arrays to be first processed by all of the processors from the main storage in parallel. Then, the same operation is performed on another array. Subsequently, in the above-mentioned manner, remaining elements of the arrays are read from one array to another. A partial element group thus read sequentially is stored in the plurality of preload register groups in distributed manner. According to a load request issued from each processor, the array elements preloaded in the preload register groups corresponding to that processor are read in the order the array elements were preloaded.

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