Data processor providing plural decoders for effecting fast regi

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3642627, 3642628, 3649465, 3649466, 364DIG2, G06F 930, G06F 9308

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active

051135035

ABSTRACT:
A data processor has an execution unit, an instruction register in which macro instructions having a register field are set for specifying registers in the execution unit, a micro ROM in which micro instructions containing a register instruction field are set, a first decoder for decoding the register specification data from the instruction register, a second decoder for decoding the register specification data from the micro ROM, and a selector for selecting either of the output of the first decoder or that of the second decoder corresponding to the selection signals provided from the micro ROM and thus producing data for specifying the registers. In this data processor having such a configuration, the decodings of the two register specification data described above are carried out substantially in parallel and a high-speed operation is thus made possible.

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patent: 4674063 (1987-06-01), Sato
patent: 4812972 (1989-03-01), Chastain et al.
patent: 4873629 (1989-10-01), Harris et al.

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