Data processor microsequencer having multiple microaddress sourc

Details Data processor microsequencer having multiple microaddress sourc Data processor microsequencer having multiple microaddress sourc

1993-02-08

1993-08-31

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 3642318, 3642624, 364262, 364 8, 364263, G06F 922, G06F 938

Patent

active

052416372

ABSTRACT:
A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.

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Neil H. E. West and Kamran Eshraghian, "Principles of CMOS VLSI Design--A Systems Perspective," Addison-Wesley Publishing Company, Oct. 1985, pp. 368-379.

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