Data processor in which external sync signal may be selectively

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364DIG1, 3642711, 3642328, G06F 1300, G06F 104

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active

051796945

ABSTRACT:
An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

REFERENCES:
patent: 3962683 (1976-06-01), Brown et al.
patent: 4112490 (1978-09-01), Pohlman et al.
patent: 4153933 (1979-05-01), Blume, Jr. et al.
patent: 4462072 (1984-07-01), Tague et al.
patent: 4503490 (1985-03-01), Thompson

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