Data processor implementing a two's complement addressing techni

Details Data processor implementing a two's complement addressing techni Data processor implementing a two's complement addressing techni

1994-01-14

1995-07-18

Harvey, Jack B.

Boots, shoes, and leggings

364DIG1, G06F 1200

Patent

active

054349885

ABSTRACT:
The data processor accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under the user mode being able to easily be detected.

REFERENCES:
patent: 3571803 (1971-03-01), Huttenhoff
patent: 3786436 (1974-01-01), Zelinski et al.
patent: 3858183 (1974-12-01), Amdahl et al.
patent: 3924245 (1975-12-01), Eaton et al.
patent: 3970999 (1976-07-01), Elward
patent: 4087856 (1978-05-01), Attanasaio
patent: 4089052 (1978-05-01), Gruner
patent: 4099242 (1978-07-01), Houston et al.
patent: 4184201 (1980-01-01), Melberg et al.
patent: 4206503 (1980-06-01), Woods et al.
patent: 4267458 (1981-05-01), Uram et al.
patent: 4296467 (1981-10-01), Nibby, Jr.
patent: 4296469 (1981-10-01), Gunter et al.
patent: 4312034 (1982-01-01), Gunter et al.
patent: 4402044 (1983-08-01), McDonough et al.
patent: 4451880 (1984-05-01), Johnson et al.
patent: 4584666 (1986-04-01), Zolnowsky
patent: 4713749 (1987-12-01), Magar et al.
patent: 4779187 (1988-10-01), Letwin
patent: 5021991 (1991-06-01), MacGregor
patent: 5140684 (1992-08-01), Sakamura et al.
patent: 5327542 (1994-07-01), Sakamura et al.
Intel Advance Information 8036 High Performance Microprocessor with Integrated Memory Management, Intel Corp., Oct., 1985.
32-bit MPU Virtual Storage Management Diffuses by Means of 68030, Nikkei Electronics, Sep., 1987.
Sakamura, "Method of Allocation of Order Bit in a Tip for TRON," Materials for Realtime Architecture TRON Research Meeting, Oct. 1, 1987.
Motorola, "M68000 8-/16-/32-Bit Microprocessors User's Manual," 7th Ed., 1989.

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