Data processor having integrated boolean and adder logic for acc

Details Data processor having integrated boolean and adder logic for acc Data processor having integrated boolean and adder logic for acc

1998-06-05

2000-05-30

Follansbee, John A.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 750

Patent

active

06070182&

ABSTRACT:
An application accelerator unit (AAU) that is integrated as part of a data processor, such as an I/O processor (IOP) integrated circuit. In one embodiment, the AAU includes logic for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). The AAU performs boolean operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is then written to the redundant disk array. Additionally, the AAU may feature adder logic configured to perform an addition such as a network header checksum calculation on each data packet. The AAU includes a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating storage and networking applications as well as for local memory DMA-type transfers, using the chain descriptor construct.

REFERENCES:
patent: 4701876 (1987-10-01), McCanny et al.
patent: 5025408 (1991-06-01), Sherman
patent: 5235537 (1993-08-01), McWhirter et al.
patent: 5465224 (1995-11-01), Guttag et al.
patent: 5745125 (1998-04-01), Deering et al.

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