Boots – shoes – and leggings
Patent
1991-02-04
1993-05-11
Bowler, Alyssa H.
Boots, shoes, and leggings
364DIG1, 3642436, 3649642, 365 49, G06F 1208, G06F 1204, G11C 700
Patent
active
052108422
ABSTRACT:
A data processor having an instruction varied set associative cache boundary access capability provides reduced power consumption and maintains data processor performance. Queued data processor operation codes are partially decoded within an intermediate stage of an instruction pipe of the data processor to provide information on pending instructions. The information provided determines if a pending instruction will require either a full or a partial output line of information from the set associative cache. When the provided information from the instruction pipe indicates that an instruction will require a full output line of information to complete execution, the set associative cache provides the full output line of information. Otherwise, the set associative cache provides only a partial output line of information.
REFERENCES:
patent: 4575792 (1986-03-01), Keeley
patent: 4833642 (1989-05-01), Ooi
patent: 4905141 (1990-02-01), Brenza
patent: 4942520 (1990-07-01), Langendorf
patent: 4945512 (1990-07-01), Dekarske et al.
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5091851 (1992-02-01), Shelton et al.
Bowler Alyssa H.
King Robert L.
Motorola Inc.
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