Data processor having an instruction decoder and a plurality of

Details Data processor having an instruction decoder and a plurality of Data processor having an instruction decoder and a plurality of

1998-04-08

2000-09-05

Lim, Krisna

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

712208, 712209, 712212, G06F 330

Patent

active

061158062

ABSTRACT:
In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.

REFERENCES:
patent: 5202967 (1993-04-01), Matsuzaki et al.
patent: 5321821 (1994-06-01), Itomitsu et al.
patent: 5371864 (1994-12-01), Chuang
patent: 5442762 (1995-08-01), Kato et al.
patent: 5761470 (1998-06-01), Yoshida
"Performance Evaluation of Superscalar Processor, "SHIMPU" based on the SIMP (Single Instruction Stream/Multiple Instruction Pipeline Architecture", JSSP "Parallel Processing Symposium", '90, May 1990, pp. 337-344, by Kuga et al., (Interdisciplinary Graduate School of Engineering Sciences, Kyushu University).

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