Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
Reexamination Certificate
2000-02-22
2002-05-28
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding by plural parallel decoders
C712S210000
Reexamination Certificate
active
06397323
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processor for performing a plurality of operations in parallel, and more particularly to a data processor for performing a plurality of operations in parallel at a high efficiency by executing a so-called VLIW (Very Long Instruction Word) type instruction which specifies a plurality of operations by one instruction.
2. Description of Related Art
As a data processor for performing operations at a high speed utilizing parallelism of instruction levels, data processors adopting superscalar type or VLIW type parallel operation techniques have been already proposed. So-called superscalar is a parallel operation technique in which parallelism of instruction levels is detected by hardware from an instruction stream and a plurality of instructions are then executed in parallel.
On the other hand, the VLIW technique is a parallel operation technique in which one instruction consists of a plurality of parallel executable operations which are detected and encoded by a compiler at compiling time. A plurality of operations which are specified by this long instruction word are executed in parallel. These types of conventional data processors are described in detail in “Instruction-Level Parallelism”, B. R. Rau and J. A. Fisher, The Journal of Supercomputing, Vol. 7, No. 1/2, 1993, for example.
The conventional superscalar type data processor is advantageous in being capable of executing instructions that were generated in the past without translating. However, since the number of instructions which are executable in parallel is not constant, it is necessary to specify instructions which are executable in parallel or to align instructions which are to be inputted to an instruction decoder in accordance with the number of instructions which are executable in parallel. This imposes a large load on the decoder hardware.
Further, since the conventional VLIW type data processor guarantees that instructions have the same length and all of a plurality of operations which are described within one instruction can be executed in parallel, the problem of an increased load on the decoder hardware is not generated unlike in the conventional superscalar type data processor as mentioned above. However, since the conventional VLIW type data processor consumes one instruction even when there is no operations which can be executed in parallel, a number of operation fields specifying null operations (No Operation: NOP) are generated, whereby the amount of instruction code becomes very big. In addition, in the conventional VLIW type data processor, types of operations which can be specified by respective operation fields are limited to simplify the instruction decoder and the operation mechanism. Because of the standardized method of specifying operation, flexibility of assigning operations within one instruction is small, and therefore the instruction code efficiency is poor.
SUMMARY OF THE INVENTION
The present invention has been made to overcome these disadvantages of the prior art as mentioned above. The present invention therefore aims to obtain a data processor which is basically of the VLIW type but achieves an improved instruction code efficiency, in which the necessity of specifying null operations is reduced by flexibly controlling the number and the order of operations, using a format field which specifies the number of the operation fields and the order of the operations. At the same time, decoders decode only operations of specific functions depending on executing mechanisms in parallel. With decoding the respective operation fields by a number of simple decoders, the present invention increases the number of operations which can be specified by the respective operation fields.
A data processor according to the present invention comprises: an instruction decoder for decoding an instruction code consisting at least one operation field which specifies the type of an operation to be executed and a format field which specifies the number of the operation fields and outputting control signals; and a plurality of operating means which are connected to the instruction decoder for executing the instruction in accordance with the control signals outputted from the instruction decoder. In the data processor, when the instruction decoder decodes a first instruction code which includes a first number of operation fields, the instruction decoder outputs a first set of control signals, and the plurality of operating means execute the first number of operations in accordance with the first set of control signals, and when the instruction decoder decodes a second instruction code which includes a second number of operation fields and has the same code length with the first instruction code, the second number being different from the first number, the instruction decoder outputs a second set of control signals different from the first set of control signals, and the plurality of operating means execute the second number of operations in accordance with the second set of control signals.
A data processor according to the present invention comprises: an instruction decoder for decoding an instruction code; a control unit which is connected to the instruction decoder to output control signals in accordance with decoded results by the instruction decoder; and first operating means and second operating means which are connected to the instruction decoder for executing an instruction in accordance with the control signals outputted from the control unit. In the data processor, when the instruction decoder decodes an instruction code which consists of at least a first operation field and a second operation field, each specifying an operation to be executed, and a format field which specifies the number of operation fields and the order of executing operations specified by the operation fields, the control unit outputs a first control signal and a second control signal in accordance with the order of executing operations specified by the format field and operation types specified by the first operation field and the second operation field, the first operating means executes the first operation in accordance with the first control signal, and the second operating means executes the second operation in accordance with the second control signal.
In the data processor having the configuration as mentioned above, when the instruction decoder decodes a first instruction code in which sequential execution of the first operation specified by the first operation field and the second operation specified by second operation field is specified by the format field, the instruction decoder outputs a first decoded result while the control unit outputs the first control signal at a first time point and then outputs the second control signal at a second time point in accordance with the first decoded result, so that the first operating means executes the first operation in accordance with the first control signal and the second operating means thereafter executes the second operation in accordance with the second control signal, and when the instruction decoder decodes a second instruction code in which simultaneous execution of a third operation specified by the first operation field and a fourth operation specified by the second operation field is specified by the format field, the instruction decoder outputs a second decoded result while the control unit outputs a third control signal and a fourth control signal at the same time in accordance with the second decoded result, so that the first operating means and the second operating means simultaneously execute the third operation and the fourth operation in accordance with the third control signal and the fourth control signal, respectively.
A data processor according to the present invention comprises: a first decoder for decoding a predetermined field of an instruction code and outputting a control signal; a first operation execution unit which is connected to the first decoder to operate in
Burns Doane , Swecker, Mathis LLP
Chang Jung-won
Maung Zarni
Mitsubishi Denki & Kabushiki Kaisha
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