Data processor having an address translation buffer operable wit

Details Data processor having an address translation buffer operable wit Data processor having an address translation buffer operable wit

1995-09-07

1998-08-18

Swann, Tod R.

Boots, shoes, and leggings

395455, 395403, 364DIG1, G06F 1210

Patent

active

057969787

ABSTRACT:
A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

REFERENCES:
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patent: 5123101 (1992-06-01), Sindhu
patent: 5222222 (1993-06-01), Mehring et al.
patent: 5263140 (1993-11-01), Riordan
patent: 5465337 (1995-11-01), Kong
"Very High Speed MOS Device," published by Baifu-Kan, Ltd., Feb. 10, 1986, pp. 287-288.

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