Data processor having a timer circuit for performing a buffered

Details Data processor having a timer circuit for performing a buffered Data processor having a timer circuit for performing a buffered

1993-05-18

1996-07-09

Lim, Krisna

G06F 104

Patent

active

055353762

ABSTRACT:
A timer (28) uses two output-compare timer channels to form a buffered pulse width modulator. A first register (62) and a second register are provided to store a first pulse width value and a second register (66), respectively. When the first register (62) is written to, a select control circuit (68) provides the first pulse width value stored therein to a channel input/output circuit (70). When the second register (66) is written to, the select control circuit (68) provides the second pulse width value stored therein to the channel input/output circuit (70). The select control circuit (68) provides one of the first and second pulse width values such that the signal output by the channel input/output circuit (70) is not erroneous. By writing a new pulse width value to a register associated with an unused channel, the pulse width modulation function is buffered.

REFERENCES:
patent: 4222103 (1980-09-01), Chamberlin
patent: 4618968 (1986-10-01), Sibigtroth
patent: 4910671 (1990-03-01), Kitamura et al.
patent: 4926319 (1990-05-01), Wilkie et al.
patent: 4942522 (1990-07-01), Wilkie et al.
patent: 5436853 (1995-07-01), Shimohara
"M68300 Family TPU Time Processor Unit Reference Manual", published by Motorola, Inc., in 1990, pp. 3-34 to 3-56.
"M68HC11 Reference Manual"published by Motorola, Inc. in 1989, pp. 10-34, 10-36, and 10-21.

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