Data processor having a multi-stage instruction pipe and selecti

Details Data processor having a multi-stage instruction pipe and selecti Data processor having a multi-stage instruction pipe and selecti

1993-06-21

1994-01-04

Dixon, Joseph L.

Boots, shoes, and leggings

395750, 3649486, 3642318, 364262, 3642624, 364263, 364DIG1, G06F 900, G06F 922, G06F 938

Patent

active

052768244

ABSTRACT:
A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.

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