Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1997-07-03
2004-06-29
Dinh, Dung C. (Department: 2153)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C711S001000, C710S307000
Reexamination Certificate
active
06757809
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processor, and more in particular it relates to a data processor capable of reducing the time required for task switching by saving and returning contents of registers to and from a memory for task switching at high speed.
2. Description of Related Art
With recent higher operation speed of the data processor, there has been required higher operation speed of a main memory, as a result, there occurs a problem that a cost price is increasing to realize the system of such a memory. As one method for solving such a problem, there is employed an art to provide a cache memory, which is a high-speed memory, between the data processor and the main memory in order to fill up the difference of the operation speed between the data processor and the main memory.
In addition to the above art, there is disclosed in detail in Japanese Patent Application Laid-Open No.63-193230 (1988), for example that the high-speed cache memory is realized by providing it in the same integrated circuit of the data processor.
However, even when only the average time required for memory access is reduced by providing the cache memory, in the case where there is carried out task switching or the like which is specifically requested to operate at high-speed, there is possibility that a cache miss should be occurred, which resulting in no possibility to reduce the maximum value of the time required for task switching operation.
In order to solve such a problem, there is proposed such arrangement as that a context saving memory for task switching operation is defined in addition to a normal memory space, and the memory to be used as context saving memory space is constructed to be a high-speed memory or the context saving memory is realized in the same integrated circuit of the data processor, and then, the time required for task switching can be reduced. Such art as described above are disclosed in the Japanese Patent Application Laid-Open No. 64-91253 (1989), for example.
Even when the high-speed memory is provided as the cache memory, in the case where a cache miss should be occurs, it is not possible to realize high-speed memory access. And even when there is defined, in addition to the normal memory apace, another memory space for context saving, unless this memory which constructs the memory space for context saving is capable of being operated at higher speed than other memories, the time required for task switching can not be reduced.
Such a problem occurs because a content of only one register can be transferred by one operation at saving the content of a register in the memory or at restoring it by the context switching instruction.
Especially, in the construction in which the cache memory and the data processor are built in the same integrated circuit, data transfer path between the cache memory and the register file can be provided by low cost, so that it is easy to increase capacity of data transferring by widening bit width of the path.
SUMMARY OF THE INVENTION
The forgoing problem is solved in accordance with the present invention. The primary object of the present invention is to provide a data processor in which time needed for task switching is reduced by performing data transfer between the register and the memory by two data in one operation.
The data processor of the present invention is provided with an address register which outputs address to an operand access unit (memory access unit), a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register and which simultaneously transfers two data by control of an instruction execution control unit.
In the data processor of the present invention, in the case where an LDCTX instruction which is the instruction for loading data to more than two register from the memory is executed, according to control of the instruction execution control unit, a combined data of two data each of which is to be loaded in different register is transferred from the operand access unit to the data register, and an high order 4 bytes and low order 4 bytes of the data register are simultaneously transfers to two register through two data transfer paths, respectively.
Also, in the case where an STCTX instruction which is the instruction for storing data from more than two register to the memory is executed, according to control of the instruction execution control unit, contents of the two registers are simultaneously transferred to a high order 4 bytes and a low order 4 bytes of the data register, respectively, and two data are combined into one data in the data register, thereafter the combined data is transferred to the operand access unit in one memory accessing.
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patent: 64-91253 (1989-04-01), None
Eggebrecht, Lewis “Interfacing to the IBM Personal Computer”, 2nd.edition, 1990 Howard W. Sams & Company, pp. 45-88.*
Duntemann, Jeff, “Assembly Language Step-by-Step” 2nded. Chapter 6, “16-bit and 32-bit registers” excerpt from books24x7.com.*
“Variable Channel Bandwidth”, IBM TDB v25 iss3b Aug. 1982,.
Burns Doane Swecker & Mathis L.L.P.
Dinh Dung C.
Renesas Technology Corp.
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