Data processor for selective simultaneous execution of a delay s

Details Data processor for selective simultaneous execution of a delay s Data processor for selective simultaneous execution of a delay s

1991-07-09

1995-01-10

Kim, Ken S.

Boots, shoes, and leggings

3642615, 3642292, 3649381, 3649483, 364DIG1, 395800, G06F 938

Patent

active

053815319

ABSTRACT:
An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.

REFERENCES:
patent: 3718912 (1983-02-01), Hasbrouck et al.
patent: 4847748 (1989-07-01), Yamahata et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928226 (1990-05-01), Kamada et al.
patent: 4942525 (1990-07-01), Shintani et al.
patent: 5051896 (1991-09-01), Lee et al.
patent: 5072364 (1991-12-01), Jardine et al.
patent: 5185868 (1993-02-01), Tran
patent: 5233694 (1993-08-01), Hotta et al.
patent: 5269007 (1993-12-01), Hanawa et al.
Miller, R. E., et al. "Floating-Duplex Decode and Execution of Instruction," IBM Technical Disclosure Bulletin, vol. 23, No. 1, Jun. 1980, pp. 409-412 (English).
"Machine Which Reduces Delay Penalties due to Data Dependencies and Interlocks to Achieve High Performance," IBM Technical Disclosure Bulletin, vol. 27, No. 10A, Mar. 1985 (one page) (English).

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