Data processor for reloading deferred pushes in a copy-back data

Details Data processor for reloading deferred pushes in a copy-back data Data processor for reloading deferred pushes in a copy-back data

1990-02-26

1993-03-23

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642431, 3649642, 3649645, G06F 1212

Patent

active

051971445

ABSTRACT:
A data processor is provided for reloading deferred pushes in copy-back cache. When a cache "miss" occurs, a cache controller selects a cache line for replacement, and request a burst line read to transfer the required cache line from an external memory. When the date entries in the cache line selected for replacement are marked dirty, the cache controller "pushes" the cache line or dirty portions thereof into a buffer, which stores the cache line pending completion, by a bus interface controller, or the burst line read. When the burst line read terminates abnormally, due to a bus error or bus cache inhibit (or any other reason), the data cache controller reloads the copy-back cache with the cache line stored in the buffer. The reloading of the copy-back cache avoids the potential for multiple concurrent exception conditions, and eliminates the problem of unnecessarily removing an otherwise valid cache entry from the cache.

REFERENCES:
patent: 4394733 (1983-07-01), Swenson
patent: 4445177 (1984-04-01), Bratt et al.
patent: 4523206 (1985-06-01), Sassler
patent: 4598357 (1986-07-01), Swenson et al.
patent: 4858111 (1989-08-01), Steps

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