Data processor for processing instruction after conditional bran

Details Data processor for processing instruction after conditional bran Data processor for processing instruction after conditional bran

1994-03-31

1995-05-30

Bowler, Alyssa H.

Boots, shoes, and leggings

395425, 395375, 3642318, 364240, 364253, 3642615, 364DIG1, G06F 934, G06F 1212, G06F 1578

Patent

active

054210267

ABSTRACT:
A data processor includes a first circuit for decoding a sequence of instruction including a conditional branch instruction in such a manner that said conditional branch instruction is decoded and an instruction fetched after said conditional branch instruction is decoded before a branch condition for said conditional branch instruction has not decided. Said first circuit generates an operand address for the decoded instruction and a first signal indicating that said operand address is one generated before a branch condition is decided. A second circuit generates, after decision of said branch condition, a second signal indicating whether or not an instruction decoded after said conditional branch instruction is executed. The bus interface circuit performs replacement of a content of an associative memory. A control circuit receives the first and second signals and operates to hold replacement of a content of the associative memory.

REFERENCES:
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patent: 4742451 (1988-05-01), Bruckert et al.
patent: 4760520 (1988-07-01), Shintani et al.
patent: 4942520 (1990-07-01), Langendorf
patent: 5053954 (1991-10-01), Miyoshi
patent: 5081574 (1992-01-01), Larson et al.
patent: 5129068 (1992-07-01), Watanabe et al.

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