Data processor for parallelly executing conflicting instructions

Details Data processor for parallelly executing conflicting instructions Data processor for parallelly executing conflicting instructions

1987-11-24

1990-05-22

James, Andrew J.

Boots, shoes, and leggings

G06F 938, G06F 900, G06F 738

Patent

active

049282263

ABSTRACT:
A data processor includes an instruction detection unit for detecting that a succeeding instruction writes a read-out operand into a general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by an instruction hold unit; a conflict detection unit for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.

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patent: 4638429 (1987-01-01), Watabe et al.
patent: 4639886 (1987-01-01), Hashimoto et al.
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patent: 4736288 (1988-04-01), Shintani et al.
patent: 4739470 (1988-04-01), Wada et al.
patent: 4752873 (1988-06-01), Shorai et al.
Research disclosure, "Look-ahead and Instruction, Operand Queue Technique", Oct. 1987, No. 282, p. 28231.
Research disclosure, "Register and Operand Conflict Mechanism", Oct. 1987, No. 282, p. 28234.

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