Data processor for executing data saving and restoration registe

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395250, 395425, 395775, 395375, 364DIG1, 3642808, 3642302, 3642545, 3642632, G06F 1300

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052416798

ABSTRACT:
A data processor comprises a plurality of registers 1 (registers a to d), a plurality of data saving stack memory devices 2 coupled to the registers 1 for exclusive use thereof, respectively, and an instruction decoder for decoding instructions for controlling the registers 1 and the data saving stack memory devices 2 in accordance with the result of the instruction decoding. In response to an instruction "PUSH", the contents of the registers 1 (registers a to d) are selectively saved to the data saving stack memory device 2. In response to a instruction "POP", the contents of the data saving stack memory devices 2 are selectively restored to the registers 1 (registers a to d). Each of the instructions "PUSH" and "POP" has a field for indicating need or needlessness of the saving and restoration for each of the registers 1 and each of the data saving memories 2.

REFERENCES:
patent: 4268904 (1981-05-01), Suzuki et al.
patent: 4740893 (1988-04-01), Buchholz et al.
patent: 5041964 (1991-08-01), Cole et al.
patent: 5095526 (1992-03-01), Baum
Motorola MC 68020 User's Manual, Prentice-Hall Inc., 1984 Appendix B, pp. 110-112.

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