Data processor for concurrent executing of instructions by plura

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3642287, 3642318, 36493141, 36494834, 36494832, G06F 938

Patent

active

049425250

ABSTRACT:
An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.

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patent: 4858105 (1989-08-01), Kuriyama et al.
R. M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, 1967 Jan., pp. 25-33.

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