Data processor execution unit which receives data with reduced i

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364746, G06F 738, G06F 772

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active

047440430

ABSTRACT:
A data processor execution unit is provided for coupling multiple operands to an AU in response to an operand selection portion of an instruction supplied from an instruction register. At least two operands are provided from two pluralities of registers, respectively. Additionally, a predetermined one of the operands contains encoded information for selecting one of a plurality of arithmetic operations which the AU performs. The operand containing the encoded information is coupled to an AU control decoder for use in controlling the operation of the AU. In one form, a single operand selection portion of an instruction selects a plurality of registers containing operands which the AU may utilize. In another form, one of the operands contains encoded information for use in selecting arithmetic formats of the AU.

REFERENCES:
patent: 3909789 (1975-09-01), Holtey et al.
patent: 4121298 (1978-10-01), Akushsky et al.
patent: 4384340 (1983-05-01), Tague et al.
"DSP Microprocessor ADSP-2100" pp. 1-35 Analog Devices, Digital Signal Processing Division, Norwood, MA Aug. 1986.
"Modular Arithmetic . . . An Ancient Science for a New Computer" Westinghouse Engineer vol. 23, No. 4, Jul. 1963 pp. 112-114.

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