Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
1995-11-09
2001-01-23
Follansbee, John A. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S206000, C712S212000
Reexamination Certificate
active
06178492
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processor realizing a high processing capability by a parallel processing mechanism, and, more particularly, relates to a data processor capable of executing a plurality of instructions in parallel.
2. Description of the Related Art
In recent years, together with its high processing speed resulting from the improvement of operating frequency, a data processor is making a remarkable progress in performance due to the development of parallel processing techniques such as pipeline processing or superscalar techniques. A superscalar technique is a technique for decoding and executing a plurality of instructions in parallel. For example, Japanese Patent Application Laid-Open No. 3-91029 (1991), discusses a data processor which decodes and executes, in parallel, two instructions with no operand interference. The data processor uses a superscalar technique that cannot execute certain combinations of instructions in parallel such as instructions having an operand interference or instructions whose operand is a memory operand. A key to the improvement of performance is in increasing the combination of instructions capable of being executed in parallel.
In a conventional data processor, in most cases, two instructions whose operands are interdependent are not executed at the same time by simply connecting operators in series.
Known data processors execute two instructions having operand interference in parallel by serially connecting ALU's in two steps or by simply connecting operators in series. However, it is difficult to obtain a high speed operation and to improve the operating frequency of the data processor.
In order to execute, in parallel, two instructions having a memory operand or whose operand is a memory operand, it is necessary to execute two memory accesses in parallel. In order to access the two independent memory operands in parallel, it is necessary to provide two ports on a main memory or a cache memory, or to have an interleaved memory by providing multi-ports on only a tag memory of a built-in cache. In a conventional data processor having such a configuration, in order to execute in parallel the two instructions having two memory operands, a large amount of hardware must be added and the control becomes complicated.
In such a way, in order to improve the performance of the data processor by using a superscalar system, it is important to increase the combination of the instructions executable in parallel. However, as mentioned above, it is difficult to execute, in parallel, the two instructions having operand interference at high speed. Also, in order to execute two instructions accessing the memory in parallel, a large amount of hardware is required.
SUMMARY OF THE INVENTION
The present invention has been devised in view of such circumstances and disadvantages of know data processors. It is an object of the present invention to provide a data processor which improves performance by using a superscalar system, by executing two instructions having operand interference at high speed in parallel or two instructions accessing storing means in parallel without increasing an amount of hardware considerably. It is also an object of the present invention to provide a data processor in which the combination of instructions executable in parallel is increased.
A first aspect of the data processor applies to a shift instruction as a first instruction, and an arithmetic operation, a logical operation or a comparing instruction as a second instruction. Instruction executing means includes composite operating means having a shifter executing a shift processing for only one or a plurality of predetermined shift count values, and operating means, whose, at least, one input is connected to an output of the shifter, for executing, at least, either the arithmetic operation or logical operation. Instruction decoding means includes means for decoding instructions of an instruction group consisting of a plurality of instructions including the first instruction and the second instruction succeeding the first instruction. Furthermore, there is provided judging means for judging whether or not a first condition, in which the first instruction is a shift instruction executing the shift processing of a shift count value which can be executed by the shifter, and a second condition, in which the second instruction is an instruction executing the operation executable by the operating means, and the second instruction refers to a shift result of the first instruction, are satisfied.
A second aspect of the data processor applies to an arithmetic operation or a logical operation instruction as a first instruction, and a shift instruction as a second instruction. Instruction executing means includes composite operating means having operating means for executing, at least, either the arithmetic operation or the logical operation, and a shifter, whose input is connected to an output of the operating means, for executing a shift processing for only one or a plurality of predetermined shift count values. Instruction decoding means includes means for decoding instructions of an instruction group consisting of a plurality of instructions including the first instruction and the succeeding second instruction. Furthermore, there is provided judging means for judging whether or not a first condition, in which the first instruction is an instruction executing an operation executable by the operating means, and a second condition, in which the second instruction is the shift instruction executing a shift processing of any shift count value executable by the shifter, and the second instruction refers to an operation result of the first instruction, are satisfied.
A third aspect of the data possessor applies to an operation instruction as a first instruction, and a register—register transfer instruction as a second instruction. Instruction executing means includes operating means for executing, at least, one of an arithmetic operation, a logical operation and a shift processing, and data transferring means for transferring an operation result of the operating means to a plurality of registers. Instruction decoding means includes means for decoding instructions of an instruction group consisting of a plurality of instructions including the first instruction and the succeeding second instruction. Furthermore, there is provided judging means for judging whether or not a first condition, in which the first instruction is an instruction executing an operation executable by the operating means, and transferring the result to a register corresponding to a first value included in itself, and a second condition, in which the second instruction is an instruction transferring the operation result of the first instruction to a register corresponding to a second value included in itself, are satisfied.
A fourth aspect of the data processor applies to an operation instruction as both a first and a second instructions. Instruction executing means includes first and second operating means for respectively executing, at least, one of an arithmetic operation, a logical operation and a shift processing, and data transferring means for transferring a operation result of the first operating means and an operation result of the second operating means respectively to the different registers in parallel. Instruction decoding means includes means for decoding instructions of an instruction group consisting of a plurality of instructions including the first instruction and the succeeding second instruction. Furthermore, there is provided judging means for judging whether or not a first condition, in which the first instruction is an instruction executing an operation executable by the first and second operating means and transferring a result to a register corresponding to a first value included in itself, and a second condition, in which the second instruction is an instruction transferring an operation result of the first instruction to a
Davis Jr. Walter D.
Follansbee John A.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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