Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2001-06-22
2004-08-17
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S036000, C712S211000, C712S245000, C712S248000, C711S123000, C711S125000, C711S128000, C711S133000, C711S135000, C711S144000, C711S145000, C711S205000, C711S206000, C711S207000
Reexamination Certificate
active
06779102
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processor capable of processing instructions at a high speed.
The data processor of the prior art comprises, as shown in
FIG. 1
, an interface circuit
7
for data transfer with a main memory
5
, an instruction control unit
3
for controlling an instruction to be executed, and an instruction execution unit
4
for executing the instruction. When an instruction read out from the main memory
5
is transferred to an instruction control unit
3
via a line
73
, the interface circuit
7
and a line
11
, the instruction control unit
3
analyzes the instruction and transfers the result to the instruction execution unit
4
over a line
15
. (It will be recognized that lines
73
,
11
and
15
along with others to be described herein include more than one wire and are actually buses. Thus, the use of the term “line” herein includes both single conductors and multiple conductors.) As a result of the analysis, the instruction execution unit
4
generates a variety of control signals so that respective gates in the instruction execution unit
4
are opened or closed by those control signals to execute processing such as arithmetic operation, storage or shift. An instruction designates an address via lines
14
and
74
to read out data from the main memory
5
via lines
13
and
73
or write the arithmetic result in the main memory
5
. The instruction control unit
3
designates the read address of a subsequent instruction in the main memory
5
via a line
12
, the interface circuit
7
and the line
74
. By repeating a series of those operations, data processor
1
executes the program which is stored in the main memory
5
.
This processor of the prior art is equipped with a cache memory
71
to allow reading data from the main memory
5
at high speed. The cache memory
71
is addressed by the address on line
74
so that the data in the corresponding entry are read out but the main memory
5
is not accessed when the cache memory
71
is accessed. Consequently, when data are read out from the cache memory, accessing the main memory is unnecessary, so that reading out of data is much faster than it would be without said cache memory.
This processor is exemplified by the data processor which is disclosed on pages 144 to 148 of the
Iwanami Microelectronics Course
, Vol. 5, “Microcomputer Hardare”, November, 1984.
In this processor, however, both the instruction control unit
3
and the instruction execution unit
4
use lines
73
and
74
, and the cache memory
71
jointly when pipeline control is to be effected. To prevent conflict, therefore, a selector
72
may inhibit concurrent use so that one of the units is held on standby.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data processor which can reduce conflict during access of an instruction control unit and an instruction execution unit to a main memory so as to process instructions at a high speed.
The data processor of the present invention enables parallel operation of the instruction control unit
3
and the instruction execution unit
4
to effect pipeline control.
In order to eliminate the above-specified defects, according to the present invention, the instruction control unit and the instruction execution unit are equipped with associative memories, and first access the corresponding associative memory so that they do not use common address lines and data lines, before data are present, to access the main memory. Namely, the instruction control unit has a first associative memory storing instructions read out from the main memory, and an instruction controller which reads out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory. The instruction execution unit has a second associative memory storing operand data read out from the main memory, and an instruction executor for executing the instruction by using operand data read out from the second associative memory when operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
As a result, no conflict arises between the instruction control unit and the instruction execution unit when data are present in the associative memory of a least one of the two memories. This reduces the chance of one of the units being held on standby. As a result, the instructions can be processed more rapidly.
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Hanawa Makoto
Hasegawa Atsushi
Kawasaki Ikuya
Nishimukai Tadahiko
Uchiyama Kunio
Hitachi , Ltd.
Kenyon & Kenyon
Pan Daniel H.
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