Data processor apparatus and method with selective caching of in

Details Data processor apparatus and method with selective caching of in Data processor apparatus and method with selective caching of in

1991-05-22

1994-04-05

Dixon, Joseph L.

Boots, shoes, and leggings

395400, 395375, 364DIG1, 36424342, 3642476, 3642631, G06F 1300

Patent

active

053012950

ABSTRACT:
The effective capacity of an instruction cache in a digital signal processor with a modified HARVARD architecture is enhanced by decoding a current instruction to be executed to determine whether it is a program memory data access (PMDA) instruction that requires a data transfer from the program memory when the next instruction is fetched from the program memory. If it is a PMDA instruction, the next instruction is loaded into a cache, which then provides the stored instruction each time the PMDA instruction reappears. This relieves a bottleneck resulting from a simultaneous call for both the next instruction, and datum for the current instruction, from the program memory. The cache is used only for an instruction following a PMDA instruction, and can thus have a substantially smaller capacity than previously.

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