Data processor and method for providing show cycles on a fast mu

Details Data processor and method for providing show cycles on a fast mu Data processor and method for providing show cycles on a fast mu

1994-12-05

1996-08-20

Pan, Daniel H.

Boots, shoes, and leggings

39542101, 39542104, 364DIG1, 364DIG2, G06F 1340, G06F 934

Patent

active

055487947

ABSTRACT:
A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.

REFERENCES:
patent: 4414664 (1983-11-01), Greenwood
patent: 4489380 (1984-12-01), Carey et al.
patent: 4665481 (1987-05-01), Stonier et al.
patent: 4860375 (1989-08-01), McCubbrey et al.
patent: 5339399 (1994-08-01), Lee et al.

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