Data processor and data processing method

Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal

Reexamination Certificate

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Details

C375S365000, C375S368000, C375S355000, C714S798000, C370S503000, C370S509000, C370S514000

Reexamination Certificate

active

09841077

ABSTRACT:
In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a read channel unit. The controller unit detects the predetermined mark for detecting synchronization included in the data in order to establish the synchronization of a series of data to be received from the read channel unit in order to demodulate the data other than the predetermined mark for detecting synchronization. The mark detecting unit in the controller unit detects the predetermined mark for detecting synchronization from the parallel data received with the shift register.

REFERENCES:
patent: 5631783 (1997-05-01), Park
patent: 6118603 (2000-09-01), Wilson et al.

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