Boots – shoes – and leggings
Patent
1993-01-04
1994-12-13
Mai, Tan V.
Boots, shoes, and leggings
36471504, 364745, G06F 738
Patent
active
053734610
ABSTRACT:
A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point data operand to generate a prenormalized mantissa sum. The execution unit (100) minimizes critical path delays to allow high-performance floating-point calculations while simultaneously reducing logic. Instead of treating the prenormalized mantissa sum as a 64-bit value with special treatment in case of a carry out due to overflow, the floating-point adder 100 treats the prenormalized mantissa sum as a 65-bit value, with the most significant bit being a carry output. Instead of conditionally incrementing an initial exponent value, the initial exponent value is always incremented. Thus, allowing the floating-point adder unit 100 to perform the exponent adjustments for normalization and for rounding faster.
REFERENCES:
patent: 4999803 (1991-03-01), Turrini et al.
patent: 5111421 (1992-05-01), Molnar et al.
patent: 5136536 (1992-08-01), Ng
patent: 5197023 (1993-03-01), Nakayama
Bearden David R.
Vargas Raymond L.
Mai Tan V.
Motorola Inc.
Ngo Chvong D.
Whitaker Charlotte B.
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