Data processor

Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor

Reexamination Certificate

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Reexamination Certificate

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07127589

ABSTRACT:
A data processor capable of executing sequential processing efficiently while retaining the advantages of a prior art data-driven processor. The data processor includes: an instruction fetch unit which fetches a data-driven instruction or a control-driven instruction from an instruction memory based on an input packet or a program counter; an instruction decode unit which decodes the issued instruction and, in the case of the control-driven instruction, thereafter accesses a register and performs register renaming if a data hazard is detected; a firing control unit which stores the decoded instruction in a matching memory to wait therein, and which selects one of the ready-to-fire instructions and fires the selected instruction; an execution unit which performs an operation specified by the fired instruction and, in the case of the data-driven instruction, transfers an operation result to the instruction fetch unit, or in the case of the control-driven instruction, forwards the operation result to the firing control unit; and a write back unit which writes the operation result to a register.

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Japanese Office Action dated Mar. 7, 2006 of Application No. 2003-343324.
T. Takahashi et al., “A Multi-Execution Pipeline Based on a Data-Driven Processor with Control-Driven Scheme, ” IPSJ SIG Notes, Mar. 11, 2003, vol. 2003, No. 27 (ARC-152), pp. 151-156.
K. Yasumura et al., “An Instruction Set Architecture of a Data-Driven Processor for Multimedia Networking Applications,” IPSJ SIG Notes, Mar. 11, 2003, vol. 2003, No. 27 (ARC-152), pp. 157-162.

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