Electrical computers and digital processing systems: processing – Processing architecture – Data driven or demand driven processor
Reexamination Certificate
2006-10-24
2006-10-24
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Data driven or demand driven processor
Reexamination Certificate
active
07127589
ABSTRACT:
A data processor capable of executing sequential processing efficiently while retaining the advantages of a prior art data-driven processor. The data processor includes: an instruction fetch unit which fetches a data-driven instruction or a control-driven instruction from an instruction memory based on an input packet or a program counter; an instruction decode unit which decodes the issued instruction and, in the case of the control-driven instruction, thereafter accesses a register and performs register renaming if a data hazard is detected; a firing control unit which stores the decoded instruction in a matching memory to wait therein, and which selects one of the ready-to-fire instructions and fires the selected instruction; an execution unit which performs an operation specified by the fired instruction and, in the case of the data-driven instruction, transfers an operation result to the instruction fetch unit, or in the case of the control-driven instruction, forwards the operation result to the firing control unit; and a write back unit which writes the operation result to a register.
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Ito Shinya
Kurebayashi Ryosuke
Nishikawa Hiroaki
Nomoto Shouhei
Tomiyasu Hiroshi
Coleman Eric
Semiconductor Technology Academic Research Center
Staas & Halsey , LLP
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