Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
Reexamination Certificate
2005-06-07
2005-06-07
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding by plural parallel decoders
Reexamination Certificate
active
06904514
ABSTRACT:
An instruction set is provided which has a first field for describing an execution instruction for designating content of an operation or data processing that is executed in at least one processing unit forming a data processing system, and a second field for describing preparation information for setting the processing unit to such a state that is ready to execute an operation or data processing that is executed according to the execution instruction, thereby making it possible to provide a control program having the instruction set in which preparation information independent of the execution instruction described in the first field is described in the second field. Accordingly preparation for execution of the subsequent execution instruction is made based on the preparation information. In the instruction set, since destination of branch instruction is described in the second field and is known in advance, the problems that cannot be solved with a conventional instruction set can be solved.
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English translation of International Preliminary Examination. PCT/JP00/05848.
International Search Report, International Application No. PCT/JP00/05848, Oct. 24, 2000.
Coleman Eric
IPFlex Inc.
Marshall & Gerstein & Borun LLP
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