Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
Reexamination Certificate
1999-07-23
2002-11-19
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding by plural parallel decoders
C712S216000
Reexamination Certificate
active
06484253
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a data processor of high performance, and more particularly, it relates to a data processor performing condition execution on the basis of a flag on which an operation result is reflected.
BACKGROUND TECHNIQUE
In a data processor, pipeline processing is frequently employed for improving the performance. As one of large factors hindering performance improvement in the pipeline processing, there is overhead resulting from execution of a branch. While various contrivances are made as to this, there is condition execution of an instruction as one thereof.
ARM (VLSI Technology), which is a 32-bit RISC processor, provides an execution condition specify field of four bits for instruction codes of all instructions, and can condition-execute all instructions. When executing one instruction only when a certain condition is satisfied, for example, it can be processed without causing a branch. When performing unconditional execution, one bit pattern of this field of four bits specifies regular execution.
Thus, some processors such as ARM reduce penalty of a branch by rendering many instructions condition-executable, for attaining performance improvement and reduction of power consumption. When making setting to perform condition execution in all instructions, however, fields specifying execution conditions are required for all instructions and hence the instruction length lengthens.
Particularly when ROMing and storing a program to be built in, reduction of the code size becomes important. When forcibly excessively suppressing the instruction length for reduction of the code size, an area describing actual instructions further reduces by the execution condition specify fields, and hence the number of encodable instructions reduces. Thus, when comprising condition specify fields for all instructions, there has been such a problem that the code size enlarges.
TMS320C54x series (TI), which is a 16-bit fixed-point DSP, comprises an XC instruction specifying execution of a next instruction (or subsequent two instructions) only when a condition is satisfied thereby reducing penalty of a branch. This technique requires one clock cycle for specifying the execution condition, and hence has a small effect. Further, there have been such problems that it is difficult to implement sophisticated parallel processing of a superscalar, VLIW and the like used in the processor, while an external interrupt immediately after the XC instruction is also limited.
In many data processors, an operation result or a comparison result is held as a flag in a processor status word, and this flag can be referred to as an execution condition for a condition branch instruction or a condition trap instruction. In this flag, information of a single operation result or comparison result is generally held. However, it is useful for reduction of code efficiency and reduction of penalty by a branch if a combination of a plurality of operation results or an operation result other than an immediately precedent operation can be referred to as the condition. Further, the number of registers used as those for working is also reducible.
For example, the processor Power PC (IBM) comprises a condition register consisting of eight flag groups consisting of 4-bit flags, and is contrived to be capable of specifying to which flag group to reflect the operation result in a comparison instruction and to be capable of referring to an arbitrary flag in a condition branch instruction or the like. A logical operation between the flags is also possible. However, fields for specifying a flag group storing the comparison result in the comparison instruction and the flag referred to in determination of the branch condition in the condition branch instruction are required and the instruction length lengthens by the field area. There has been such a problem that, when forcibly suppressing the instruction length, the number of instructions encodable to short instructions reduces and the code size enlarges similarly to the processor ARM.
In order to efficiently handle Boolean algebra, some processors comprise an instruction setting “1” when the condition is true or “0” when false. For example, the processor x86 series (Intel) comprises a SETcc instruction. However, there has been such another problem that, only one condition can be determined with these instructions and hence complex expressions cannot be efficiently processed when a composite condition of a plurality of condition is specified or the like.
DISCLOSURE OF THE INVENTION
The present invention has been proposed in order to solve the aforementioned problems, and aims at obtaining a high-performance data processor having excellent code efficiency, which can reduce penalty of a branch by condition execution.
It aims at obtaining a high-performance data processor implementing condition execution with an instruction set having a small instruction code size, which can reduce penalty of a branch.
A first aspect of the data processor according to the present invention is an apparatus receiving a parallel processing instruction including first and second instruction codes defining first and second instructions, which comprises a first decoder for decoding the first instruction code to output a first decoded result, a second decoder for decoding the second instruction code to output a second decoded result, flag information storage means for storing flag information, first execution control means for controlling execution of the first instruction on the basis of the first decoded result, second execution control means for controlling execution of the second instruction on the basis of the second decoded result and first execution condition judgment means for outputting second instruction execution control information which controls whether to permit or inhibit the execution of the second instruction to the second instruction execution control means on the basis of whether or not the flag information satisfies a second instruction execution condition when the first instruction is an execution condition specifying instruction defining an execution condition for the second instruction based on the flag information, and the second execution control means controls whether to permit or inhibit the execution of the second instruction on the basis of indication of the second instruction execution control information.
As in a second aspect of the data processor, it may further comprise second execution condition judgment means for outputting first instruction execution control information which controls whether to permit or inhibit the execution of the first instruction to the first execution control means on the basis of whether or not the flag information satisfies a first instruction execution condition when the second instruction is an execution condition specifying instruction defining an execution condition for the first instruction based on the flag information, and the first execution control means may control whether to permit or inhibit the execution of the first instruction on the basis of indication of the first instruction execution control information.
As in a third aspect of the data processor, the parallel processing instruction may further comprise third and fourth instruction codes defining third and fourth instructions, it may further include a third decoder for decoding the third instruction code to output a third decoded result; a fourth decoder for decoding the fourth instruction code to output a fourth decoded result; third execution control means for controlling execution of the third instruction on the basis of the third decoded result; fourth execution control means for controlling execution of the fourth instruction on the basis of the fourth decoded result; and third execution condition judgment means for outputting fourth instruction execution control information which controls whether to permit or inhibit the execution of the fourth instruction to the fourth execution control means on the basis of whether or not the flag informatio
Coleman Eric
Mitsubishi Denki & Kabushiki Kaisha
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