Data processor

Details Data processor Data processor

1997-03-05

1998-05-19

Pan, Daniel H.

Boots, shoes, and leggings

395394, 364DIG1, 364DIG2, G06F 938, G06F 940

Patent

active

057548137

ABSTRACT:
Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.

REFERENCES:
patent: 4780807 (1988-10-01), Toyoda
patent: 5093908 (1992-03-01), Beacom et al.
patent: 5155817 (1992-10-01), Kishigami et al.

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