Boots – shoes – and leggings
Patent
1979-03-20
1982-02-02
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 1306, G06F 906, G06F 700
Patent
active
043143334
ABSTRACT:
A data processor used with a host computer is constructed by a plurality of memory units, at least one arithmetic and logic unit, a register file and a microprogram memory for storing microprograms to control these circuit components. The first field of each microinstruction of the microprogram is supplied to a first logic converting circuit of which the output signal drives each memory unit. The third field of the microinstruction is supplied to the second logic converting circuit of which the output signal causes the data stored in selected registers of the register file to be supplied to the arithmetic and logic unit. The arithmetic and logic unit operates upon the data supplied in accordance with the designation by the second field, and loads the result of the operation into the register specified by one of the outputs of the second logic converting circuit. Each logic converting circuit alters, in accordance to the control signal designated from the exterior, a combination of the corresponding field of a microinstruction.
REFERENCES:
patent: 3748451 (1973-07-01), Ingwersen
patent: 3943495 (1976-03-01), Garlic
patent: 4038533 (1977-07-01), Dummermuth
patent: 4041466 (1977-08-01), Stuart
patent: 4101960 (1978-07-01), Stokes
CSP, Inc., Map a New Series of Ultrafast, Programmable, Floating Point Array Processors, 1976.
IEEE Transactions on Computers, Inner Product Computers, Jan. 1978, vol. C-27, No. 1.
Iwata Kazuhide
Okuda Nobuo
Shibayama Shigeki
Eng David Y.
Shaw Gareth D.
Tokyo Shibaura Denki Kabushiki Kaisha
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