Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Patent
1997-01-30
2000-02-08
Coleman, Eric
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
712 32, G06F 1516
Patent
active
060237570
ABSTRACT:
A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.
REFERENCES:
patent: 5699536 (1997-12-01), Hopkins
patent: 5774686 (1998-06-01), Hammond
patent: 5778423 (1998-07-01), Sites
patent: 5784636 (1998-07-01), Rupp
patent: 5794062 (1998-08-01), Baxter
Maejima Hideo
Nishimoto Junichi
Coleman Eric
Hitachi , Ltd.
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