Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Patent
1998-08-28
2000-08-29
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
710 5, G06F 938
Patent
active
061122890
ABSTRACT:
A data processor comprises an instruction decoding unit having two decoders decoding respective instructions of an instruction group consisting of a plurality of instructions including a first instruction and a second instruction succeeding the first instruction, and a judging unit judging whether or not a combination of the first instruction and the second instruction can be executed in parallel and a bus for transferring two data in parallel between an operand access unit and an integer operation unit. The data processor uses a superscalar technique. Two instructions having an operand interference can be executed in parallel at high speed and two instructions accessing a memory can be executed in parallel without considerable hardware.
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Coleman Eric
Mitsubishi Denki & Kabushiki Kaisha
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