Data processing without processor core intervention by chain...

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...

Reexamination Certificate

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C712S028000, C712S201000

Reexamination Certificate

active

07415595

ABSTRACT:
A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.

REFERENCES:
patent: 4760525 (1988-07-01), Webb
patent: 5226125 (1993-07-01), Balmer et al.
patent: 5361367 (1994-11-01), Fijany et al.
patent: 5491828 (1996-02-01), Intrater et al.
patent: 5805875 (1998-09-01), Asanovic
patent: 5987556 (1999-11-01), Nakagawa et al.
patent: 6795686 (2004-09-01), Master et al.
patent: 7159099 (2007-01-01), Lucas et al.
patent: 2002/0186043 (2002-12-01), Sihlborn
patent: 2003/0005261 (2003-01-01), Sheaffer
patent: 2003/0172249 (2003-09-01), Ganapathy et al.
patent: 2003/0212728 (2003-11-01), Dagan et al.
patent: 2004/0001296 (2004-01-01), Saito et al.
patent: 2004/0019621 (2004-01-01), Morikawa et al.
patent: 2004/0019765 (2004-01-01), Klenin
patent: 2005/0091472 (2005-04-01), Master
patent: 2005/0278502 (2005-12-01), Hundley
patent: 9749042 (1997-12-01), None
patent: 03054722 (2003-07-01), None
Nilsson, et al, “An accelerator structure for programmable multi-standard baseband processors,” Proceedings of the IAESTED Wireless Networks Conference, Jul. 2004.
Glossner, et al, “A Multithreaded Processor Architecture for SDR,” Proceedings of the Korean Institute of Communication Sciences, pp. 70-85, Nov. 2002, vol. 19, No. 11, http://ce.et.tudelft.nl/publicationfiles/625—22—sandbridge—korean—institute—paper.pdf.
Brash, “The ARM Architecture Version 6 (ARMv6)”, Jan. 2002, http://www.arm.com/support/White—Papers.
International Preliminary Report on Patentability in application No. PCT/SE2006/000602 issued Nov. 29, 2007.
International Search Report in application No. PCT/SE2006/000602.
Written Opinion in application No. PCT/SE2006/000602 mailed Sep. 15, 2006.
Corrected form PCT/ISA/237 n application No. PCT/SE2006/000602 mailed Oct. 20, 2006.

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