Data processing with first level cache bypassing after a data tr

Details Data processing with first level cache bypassing after a data tr Data processing with first level cache bypassing after a data tr

1995-03-27

1998-03-17

Swann, Tod R.

395445, G06F 1212

Patent

active

057297134

ABSTRACT:
The hit rate of a cache memory (43) is improved by monitoring data transfer commands on a command bus (51) by Non-Cache circuitry (45A). Cache data replacements are inhibited after a consecutive sequence of data transfers which exceeds a threshold number of data transfers are detected by Non-Cache circuitry (45A). The threshold number is selected to be an amount of data transfers which is large enough to imply that a large block of data is being transferred. Such large data blocks tend to flush the cache and reduce subsequent cache hit rate. Other sources of cache inhibit signals may be included, such as System Cache Enable (SKEN), to inhibit caching for other reasons, such as when non-cacheable areas such as video memory are being accessed. Inhibiting useless cache data replacements in this manner improves hit rate and reduces power consumption.

REFERENCES:
patent: 4268907 (1981-05-01), Porter et al.
patent: 4433374 (1984-02-01), Hanson et al.
patent: 4500954 (1985-02-01), Duke et al.
patent: 4701844 (1987-10-01), Thompson et al.
patent: 4740889 (1988-04-01), Motersole et al.
patent: 4942518 (1990-07-01), Weatherford et al.
patent: 5247639 (1993-09-01), Yamahata
patent: 5301295 (1994-04-01), Leary et al.
patent: 5371872 (1994-12-01), Larsen et al.
patent: 5390299 (1995-02-01), Rege et al.
patent: 5473756 (1995-12-01), Traylor
patent: 5537552 (1996-07-01), Ogasawara et al.
patent: 5539895 (1996-07-01), Bishiop
patent: 5561823 (1996-10-01), Anderson
patent: 5581731 (1996-12-01), King et al.
patent: 5594868 (1997-01-01), Nakagoshi et al.
patent: 5625793 (1997-04-01), Mirza
Bates, Ken, "I/O subsystem performanc; cache implemented in the HSC can dramatically affect disk drive performance", DEC Professional, v12, n1, p.40(7), Jan. 1993.

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