Data processing with energy-efficient, multi-divided module memo

Details Data processing with energy-efficient, multi-divided module memo Data processing with energy-efficient, multi-divided module memo

1996-10-29

1997-12-16

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523001, 36523002, G11C 700

Patent

active

056993153

ABSTRACT:
A memory architecture (11,12) includes an address bus and a plurality of address decoders (15). Each address decoder has an input which is selectively connectable to and disconnectable from the address bus.

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patent: 5301162 (1994-04-01), Shimizu
patent: 5319602 (1994-06-01), Shishikura
patent: 5430686 (1995-07-01), Tokami et al.
patent: 5450366 (1995-09-01), Watanabe
patent: 5473573 (1995-12-01), Rao

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