Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Reexamination Certificate
1999-03-31
2002-02-19
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
C712S015000
Reexamination Certificate
active
06349378
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a data processing arrangement comprising various data processors and a memory arrangement for supplying input data to the data processors and for storing output data from the data processors. Such a data processing arrangement may be used, for example, in multimedia products.
BACKGROUND ART
EP-A-0,373,714 describes a data processor comprising a plurality of parallel-operating processor elements. A coupling network couples outputs of the data processor its inputs. The coupling network comprises the following components: one or more cross-bar switches and one or more arrays of silos. A series connection is formed in which these components are alternately arranged in a succession comprising at least three elements.
SUMMARY OF THE INVENTION
It is an object of the invention to allow greater versatility of a data processing arrangement as defined in the opening paragraph.
The invention takes the following aspects into consideration. Let it be assumed that the data processing arrangement processes data in the following manner. A first data processor processes the data so as to obtain once processed data which is written into the memory arrangement. Subsequently, a second data processor reads the once processed data, processes it so as to obtain twice processed data which is written into the memory arrangement, and so on. That is, the data processors form a data processing chain. The memory arrangement provides buffer storage capacity between two successive data processors in the data processing chain.
In a data processing as described hereinbefore, there is a potential synchronization problem. A data processor may request data from the memory arrangement, whereas this data has not yet been written into the memory arrangement by a preceding data processor in the data processing chain. This synchronization problem is due to processing delays of the various data processors, or due to different processing speeds, or both.
In the background art, the synchronization problem appears to be solved in the following manner. Each data processor is programmed such that it takes into account the processing delays and the processing speeds of preceding data processors. That is, the programming of a data processor includes a correct timing of the data processing in the data processor with respect to the data processing in the preceding data processors.
The solution to the synchronization problem as described hereinbefore has the following drawback. Let it be assumed that a different data processing chain is desired. This implies that the order in which the data processors process data needs to be changed, or that one or more data processor need to carry out a different type of processing, or both. In that case, the processing delays of one or more data processors will change, or the processing speeds of one or more data processors will change, or both. Consequently, it will be necessary to re-program nearly each data processor in order to avoid a synchronization problem. This reprogramming will generally be quite complex because a data processor has to take into account the processing delays and the processing speeds of various other data processors. This is true even if one data processor only is made to carry out a different data processing. Thus, the background-art data processing arrangement is ill suited for realizing different data processing chains because this requires relatively complicated software.
In accordance with the invention, a data processing arrangement as defined in the opening paragraph, is controlled in the following manner. A configuration step and a processing step are alternately carried out. In the configuration step, the data processing arrangement is configured such that each data processor will process a block of data contained in the memory arrangement and then stop processing data. In the processing step, the blocks of data are processed in the respective data processors. A subsequent configuring step is carried out only when each data processor has processed its block of data.
Accordingly, in the invention, it can be prevented that, while the data processors process data, a data processor requests data from the memory arrangement which an other data processor has not yet written into the memory arrangement. Thus, the synchronization problem is solved. What is more, while the data processors process data, a data processor need not have knowledge of the processing delays and the processing speeds of the other data processors. Consequently, if the order in which the data processors process data is changed, it will not be necessary to re-program nearly each data processor for reasons of synchronization. Furthermore, if a data processor is re-programmed to carry out a different type of processing, it will not be necessary to re-program various others data processors. Consequently, a data processing arrangement in accordance with the invention can realize different data processing chains without this requiring relatively complicated software. Thus, the invention allows greater versatility.
The invention and additional features, which may be optionally used to implement the invention to advantage, are apparent from and elucidated with reference to the drawings described hereinafter.
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Bru Bernard
Duranton Marc
Geslin Loic
Vier Valerie
Coleman Eric
Gathman Laurie E.
U.S. Philips Corporation
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