Data processing using multiple instruction sets

Details Data processing using multiple instruction sets Data processing using multiple instruction sets

2005-11-15

2005-11-15

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

Reexamination Certificate

active

06965984

ABSTRACT:
A data processing system supports execution of both native instructions and Java bytecodes using a hardware executer for the Java bytecodes where possible and a software instruction interpreter for the Java bytecodes where these are not supported by the hardware. The sequences of native instructions26within the software instruction interpreter that perform the processing for the Java bytecodes being interpreted terminate within a sequence terminating instruction BXJ that acts differently depending upon whether or not an enabled hardware executer6is detected to be present. If an enabled hardware executer is detected as present, then the execution of the next Java bytecode is attempted with this. If an active hardware executer is not present, then the next Java bytecode is passed directly to the software instruction interpreter.

REFERENCES:
patent: 3889243 (1975-06-01), Drimak
patent: 4236204 (1980-11-01), Groves
patent: 4587632 (1986-05-01), Ditzel
patent: 4922414 (1990-05-01), Holloway et al.
patent: 4969091 (1990-11-01), Muller
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5455775 (1995-10-01), Huber et al.
patent: 5619665 (1997-04-01), Emma
patent: 5638525 (1997-06-01), Hammond et al.
patent: 5659703 (1997-08-01), Moore et al.
patent: 5740461 (1998-04-01), Jaggar
patent: 5742802 (1998-04-01), Harter et al.
patent: 5752035 (1998-05-01), Trimberger
patent: 5768593 (1998-06-01), Walters et al.
patent: 5784584 (1998-07-01), Moore et al.
patent: 5809336 (1998-09-01), Moore et al.
patent: 5838948 (1998-11-01), Bunza
patent: 5875336 (1999-02-01), Dickol et al.
patent: 5892966 (1999-04-01), Petrick et al.
patent: 5925123 (1999-07-01), Tremblay et al.
patent: 5926832 (1999-07-01), Wing et al.
patent: 5937193 (1999-08-01), Evoy
patent: 5953741 (1999-09-01), Evoy et al.
patent: 6003126 (1999-12-01), Huynh et al.
patent: 6009499 (1999-12-01), Koppala
patent: 6009509 (1999-12-01), Leung et al.
patent: 6014723 (2000-01-01), Tremblay et al.
patent: 6021469 (2000-02-01), Tremblay et al.
patent: 6026485 (2000-02-01), O'Connor et al.
patent: 6031992 (2000-02-01), Cmelik et al.
patent: 6038643 (2000-03-01), Tremblay et al.
patent: 6070173 (2000-05-01), Huber et al.
patent: 6076155 (2000-06-01), Blomgren et al.
patent: 6088786 (2000-07-01), Feierbach et al.
patent: 6122638 (2000-09-01), Huber et al.
patent: 6125439 (2000-09-01), Tremblay et al.
patent: 6148391 (2000-11-01), Petrick
patent: 6298434 (2001-10-01), Lindwer
patent: 6317872 (2001-11-01), Gee et al.
patent: 6338134 (2002-01-01), Leung et al.
patent: 6349377 (2002-02-01), Lindwer
patent: 6374286 (2002-04-01), Gee et al.
patent: 6496922 (2002-12-01), Borrill
patent: 6535903 (2003-03-01), Yates et al.
patent: 6606743 (2003-08-01), Raz et al.
patent: 2 358 261 (2001-07-01), None
patent: WO 99/18486 (1999-04-01), None
patent: 00/34844 (2000-06-01), None
patent: WO 01/61476 (2001-08-01), None
H. Stone, Chapter 12—“A Pipeline Push-Down stack Computer”, 1969, pp. 235-249.
C. Glossner et al, “Delft-Java Link Translation Buffer”, Aug. 1998.
N. Vijaykrishnan et al, “Object-Oriented Architectural Support For a Java Processor” 1998, pp. 330-355.
C. Glossner et al, “The Delft-Java engine: An Introduction”, Aug. 1997.
K. Ebcioglu et al, “A Java ILP Machine Based On Fast Dynamic Compilation”, Jan. 1997, pp. 1-13.
A. Wolfe, “First Java-specific chip takes wing”EETimes—1997.
Y. Patt,Introduction to Computer Systems From Bits and Gates to C and Beyond, 1999, pp. 1-517.
M. Ertl, “Stack Caching for Interpreters” 1994, pp. 1-13.
M. Ertl, “Stack Caching for Interpreters” 1995, pp. 1-13.
M. Ertl, “Implementation of Stack-Based Languages on Register Machines” Apr. 1996, pp. 1-4.
J. O'Connor et al, “PicoJava-I: the Java virtual Machine in Hardware”IEEE MicroA Case Intelligent RAM, Mar./Apr. 1997, pp. 45-53.
K. Andrews et al, “Migrating a CISC Computer Family Onto RISC Via Object Code Translation” 1992, pp. 213-222.
“PicoJava I Microprocessor Core Architecture” Oct. 1996, pp. 1-8, Sun Microsystems.
M. Ertl, “A New Approach to Forth Native Code Generation” 1992.
M. Maierhofer et al, “Optimizing Stack Code” 1997, p. 19.
D. Ungar et al, “Architecture of SOAR: Smalltalk on RISC” The 11thAnnual International Symposium on Computer Architecture, Jun. 1984, pp. 188-197.
O. Steinbusch, “Designing Hardware to Interpret Virtual Machine Instructions” Feb. 1998, pp. 1-59.
R. Kapoor et al, “Stack Renaming of the Java Virtual Machine” Dec. 1996, pp. 1-17.
A. Yonezawa et al, “Implementing Concurrent Object-Oriented Languages in Multicomputers”Parallel and Distributed Technology(Systems and Applications) May 1993, pp. 49-61.
C. Hsieh et al, “Java Bytecode to Native Code Translation; The Caffeine Prototype and Preliminary Results” IEEE/ACM International Symposium on Microsrchitecture, Dec. 1996, pp. 90-97.
Y. Pratt et al,Introduction to Computer Systems From Bits and Gates to C and Beyond, 2001, pp. 1-526.
Sun Microsystems PicoJava Processor Core Data Sheet, Dec. 1997, pp. 1-11.
H. McGhan et al, PicoJava A Direct Execution Engine for Java Bytecode, Oct. 1998, pp. 22-26.
C. Glossner et al, “Parallel Processing” Euro-Par 1997: Passau, Germany, Aug. 1997.
Y. Pratt,Introduction to Computer Systems From Bits and Gates to C and Beyond, 1999, pp. 10-12 & 79-82.
Espresso—The High Performance Java Core Specification, Oct. 2001, pp. 1-33, Aurora VLSI, Inc.
J. Gosling, “Java Intermediate Bytecodes” 1995, pp. 111-118.
P. Koopman, Jr. “Stack Computers The New Wave” 1989, pp. 1-234.
M. Mrva et al, “A Scalable Architecture for Multi-Threaded JAVA Applications” Design Automation and Test in Europe, Feb. 1998, pp. 868-874.
L. Chang et al, “Stack Operations Folding in Java Processors”IEEE Proc.—Comput. Digit. Tech., vol. 145, No. 5, pp. 333-340 Sep. 1998.
L. Ton et al, Proceedings of the '97 International Conference on Parallel and Distributed Systems, “Instruction Folding in Java Processor”, pp. 138-143, Dec. 1997.
K. Buchenrieder et al, “Scalable Processor Architecture for Java With Explicit Thread Support”Electronics Lettersvol. 33, No.18, pp.1532+, Aug. 1997.
C. Chung et al, Proceedings of the '98 International Conference on Parallel and Distributed Systems,“A Dual Threaded Java Processor for Java Multithreading” pp. 693-700, Dec. 1998.
I. .Kazi et al, “Techniques for Obtaining High Performance in Java Progarams” Sep. 2000, pp. 213-240.
R. Kieburtz, “A RISC Architecture for Symbolic Computation” 1987, pp. 146-155.
M. Berekovic et al, “Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications”Signal Processing Systems SIPS 98, pp. 479-488, 1997.
P. Deutsch, “Efficient Implementation of the Smalltalk-80 System” 1983, pp. 297-302.
“Rockwell Produces Java Chip” Sep. 1997, CNET News.com.
Y. Pratt et al,Introduction to Computing Systems from Bits and Gates to C and Beyond, 2001, pp. 1-16, 91-118 & 195-209.

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