Data processing unit with pipelined operands

Details Data processing unit with pipelined operands Data processing unit with pipelined operands

1986-06-11

1987-09-01

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 942, G06F 934, G06F 936

Patent

active

RE0324930

ABSTRACT:
A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.

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"VAX 11 Architecture Handbook", 1979, Digital Equipment Corp.

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